A bit error rate (“BER”) is a ratio of bits received, processed, and/or transmitted with errors to a total number of bits received, processed, and/or transmitted over a given period of time. A BER is typically expressed as ten to a negative power. If, for example, a transmission comprises 1 million bits and one of these bits is in error (e.g., a bit is a first logic state instead of a second logic state), the transmission has a BER of 10−6. The BER is useful because it may characterize the ability of a device to receive, process, and/or transmit bits.
Many devices are designed to receive, process, and then transmit a plurality of bits. An optoelectronic transceiver, for example, typically receives a plurality of bits in an electrical form and then transforms and transmits the bits in an optical form and/or receives a plurality of bits in an optical form and then transforms and transmits the bits in an electrical form.
To derive a BER for a device under test (“DUT”), bits transmitted to the DUT are compared to corresponding bits transmitted by the DUT or to corresponding bits in a pattern used to generate the bits transmitted to the DUT. In some applications, the BER of a DAT must be below a defined threshold for the DUT to pass a test.
A Bit Error Rate Test or Tester (“BERT”) is a procedure or device that establishes a BER for a DUT or to otherwise quantify a DUT's ability to receive, process, and/or transmit bits. More specifically, a BERT measures the BER of a transmission (e.g., bits transmitted, received, or processed) over a given period of time by a DUT. An exemplary BERT includes, among other components, a serializer/deserializer (“SERDES”) and a clock source fixed to a host board (e.g., PCB, circuit board, etc.). Typically, the SERDES produces serial encoded data (e.g., the bits) used to establish a BER for a DUT. More specifically, serial encoded data is transmitted from a SERDES to a DUT, which attempts to transmit the serial encoded data back to the SERDES. The SERDES compares the output of the DUT to the input to the DUT (or what the input should have been).
In order to obtain useful information from the test, bits are transmitted by the SERDES to the DUT at a specific data rate, which is controlled by the clock source. The temporal duration of a single bit (e.g., the bit period) is called the unit interval (UI). The UI is ideally the same for each bit and is equal to the reciprocal of the data rate. The data rate is set by reference to a desired use of the DUT. Until very recently, data rates did not need to exceed 1.0625 Gbps since the DUTs were not designed to operate above this data rate. Advances in technology, however, have resulted in DUTs (e.g., optoelectronic transceivers) that operate at data rates in excess of 10 Gbps.
Because of jitter typically included in data signals transmitted by a SERDES, testing DUTs at frequencies that exceed 1.0625 Gbps may not be reliable. Persons skilled in the art recognize that jitter may be defined as a deviation from the ideal timing of a digital signal event (e.g., the timing of a transition from a first logic state or bit to a second logic state or bit). The jitter j associated with a particular transition t is defined as follows j=|tidealtactual|, where j is a unit of time such as picoseconds, tideal is the time at which the transition should have occurred, and tactual is the time at which the transition actually occurred. Additionally, the root-mean-square (“RMS”) or peak-to-peak jitter for a defined number of transitions are typically employed to evaluate a device. RMS jitter is calculated using standard mathematical techniques. Peak-to-peak jitter for a defined number of transitions is typically computed as follows: jpp =(tmax−tideal)+(tideal−tmin), where jpp is peak-to-peak jitter, tideal is the time at which the transitions should have occurred, tmax is the latest time at which a transition actually occurred, and tmin is the earliest time at which a transition actually occurred. Additionally, normalized jitter or jitter in UI is obtained by dividing jitter expressed in units of time by the temporal duration of 1 UI. Normalized jitter or jitter expressed in UI is preferred since it does not depend on data rate.
Jitter is comprised of random (i.e., unpredictable) jitter and deterministic jitter. Deterministic jitter is caused by process or component interactions of a system. Random jitter is typically caused by thermal (or other random) noise effects of a system that affect the phase of the clock and/or data signals. For measurements encompassing random jitter, it is necessary to collect sufficient amounts of data to have a statistically valid jitter distribution. Histogram data of jitter should include, therefore, many thousands or millions of acquisitions to yield valid statistics.
Jitter performance of devices (e.g., a SERDES, a DUT) is specified in terms of jitter generation, jitter transfer, and jitter tolerance. Jitter generation may be defined as the amount of jitter added to a clock and/or data signal by a device. Jitter transfer is the amount of jitter present in a clock and/or data input signal received by a device that is transferred, by the device, to the clock and/or data output signal of the device. Jitter transfer may change with the data rate, so jitter transfer is typically expressed as the ratio of output jitter to input jitter at a specific data rate.
The ability of a device to correctly determine the value or state of a received data signal despite jitter is called jitter tolerance. Jitter tolerance can be defined as the amount jitter in a data signal received by a device that causes, for example, the BER of the device to exceed a specified limit. Devices that must process a digital signal (e.g., a DUT) must determine whether a sample (e.g., a voltage level) of a data signal falls within the range of a first logic state or a second logic state (e.g., a binary one or a binary zero). The device compares the sample to a reference value (e.g., a reference voltage) to determine whether the sample represents the first logic state or the second logic state. If the sample is greater than or equal to the reference value, the sample falls within the range of, for example, the first logic state, but if the sample is less than the reference value, the sample falls within the range of the second logic state. As noted above, jitter may shift the transition between logic states. As a result, the data signal may not cross the reference value in time for the device to properly determine the intended state of the sample. When this occurs, a bit error occurs. So as the magnitude of jitter is increased, the incidence of a data signal not crossing the reference value in time for a device (e.g., a DUT) to properly determine the intended state of the sample may increase as well. In other words, as the magnitude of jitter is increased the BER of the device may increase as well.
At lower data rates (e.g., at or below 1.0625 Gbps), jitter present in data signals created by an exemplary SERDES is typically not problematic. The UI of a data signal transmitted at a data rate of, for example, 1.0625 Gbps is approximately 941 picoseconds. Expressed in units of time, the peak-to-peak jitter present in a data signal created by an exemplary SERDES is in the range of 40 to 60 picoseconds, which corresponds to a peak-to-peak jitter range of 0.043 to 0.064 UI and will not mask jitter created by a DUT. In other words, the SERDES 120 may enable an accurate measurement of jitter creation and transfer by a DUT at a data rate of 1.0625 Gbps.
However, the UI of a data signal at a data rate of, for example, 10 Gbps is only 100 picoseconds. At this data rate, a peak-to-peak jitter range of 40 to 60 picoseconds corresponds to a peak-to-peak jitter range of 0.40 to 0.60 UI. This range of peak-to-peak jitter exceeds the jitter tolerance of even the most robust, functional DUTs. In other words, the SERDES 120 may not enable an accurate measurement of jitter creation and transfer by a DUT at a data rate of 10 Gbps (except as described below in connection with the present invention).
As indicated above, a typical DUT has a high jitter transfer rate and/or low jitter tolerance. The DUT may, therefore, fail a jitter test because of jitter present in a data signal transmitted to the DUT by a SERDES. In other words, jitter present in signal transmitted by a DUT may be attributed to the DUT even though the jitter was introduced into the data signal by the SERDES. Similarly, a DUT may fail a bit error rate test due entirely to the jitter introduced by the SERDES into the data signal used to test the DUT.